Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM TM), underscoring the partnership´s commitment to provide continued support to the VHDL design community.
OS-VVM delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, and provides advanced features to engineers designing ASICS and FPGA-based applications using VHDL.
The benefits of OS-VVM include:
- It provides access to advanced randomization and functional coverage capabilities (previously available only within system-level methodologies) that can be used in any testbench;
- Rather than using a constraint solver, balance in the randomization is achieved by interacting with the functional coverage model, resulting in fewer cycles;
- The initial randomization is refined by using procedural code which can easily mix directed, algorithmic, file-based methods and additional randomization; and
- Straightforward usage model, ensuring users are able to get up to speed quickly while retaining the freedom and flexibility to continue using their HDL of choice.
The latest versions of Aldec´s Active-HDL and Riviera-PRO EDA tools offer the advanced randomization and functional coverage capabilities provided by OS-VVM within the Options menu for VHDL-2008; i.e. no additional licenses are required.
SynthWorks, the maintainer of the OS-VVM packages, also offers in-depth training for OS-VVM and supplements with additional packages for creating scoreboards, memories, and abstracting interfaces.
To download the free OS-VVM packages and view additional resources, including a white paper, user guide, sample designs and VHDL package source files please visit: http://www.aldec.com/en/solutions/functional_verification/os_vvm.
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
About SynthWorks
SynthWorks provides training in leading-edge VHDL verification techniques, including transaction-based testing, bus functional modelling, self-checking, data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random, and coverage-driven random testing, and functional coverage. www.synthworks.com
